NEC CyberWorkBench

C-based High Level Synthesis and Verification Tool Set for ASIC & FPGA.

CyberWorkBench provides All-in-C synthesis and verification. Any type of module (controller or data-path) can be synthesized and verified at the C-level.

C-based Design Enables Higher Design Efficiency, Lower Area and Higher Performance of Your Chip.

Best-in-class High Level Synthesis and Verification used over 15 years for real chip design.


Advantages of CyberWorkBench:

Automatically divides source code into control and data path unit

  • Creates different architectures without modifying the source code.
  • Early time to market
  • Code size reduction (7x-10x)
  • Accelerated Simulation speed
  • Generate equivalent circuit sizes compared to hand coded RTL


One Engine for any Input Language


  • System-C and ANSI-C support


Outputs /Features:

  • Optimized RTL Circuit (VHDL/Verilog)
  • Multiple Synthesis Mode
  • Pipelining
  • Loop Merging
  • Bit-width Optimization
  • Partial Timing Constraint
  • SystemC Cycle Accurate Simulation Model
  • Fast cycle-accurate simulation model for single and multiple processes for full SoC simulation
  • ~100x Faster than RTL simulation


CyberWorkBench- FPGA Version

  • Optimized FPGA version: Altera and Xilinx
  • Automatic interface with Altera’s MegaWizard and Xilinx’s Coregen
  • Maximum use of FPGA’s DSP macros, BlockRAM
  • FPGA on-chip debugger
  • Cost effective


Best QoR

CWB achieves best QoR result because of its numerous embedded synthesis optimizations:

  • Automatic bitwidth optimization
  • Loop merging
  • Loop pipelining
  • Multiple scheduling modes
  • Overflow check
  • Parallelization of branches
  • Speculation
  • Zero cycles state transitions
  • ….and many more


Other USPs of CWB

C Source Code Debugging

  • Software-like debugging environment (look at C-code while debugging the RTL)
  • Allows break points, step and highlights lines being executed in parallel at the untimed C-code
  • Faster simulation than synthesizable RTL (~10x)


C-Based Formal Verification

  • Same formal verification methodology as in RTL-based design FASTER and EASIER


Behavioral IPs-Library:

  • Audio and Visual operations, Codec
  • Error Correction Codes, Encryption
  • Arithmetic operations
  • I/O interface

For more information, please visit : NEC CyberWorkBench


contact : [email protected]