Everyday, chip tapeouts are slipping schedule. The managers wonder why they didn’t see the issues sooner. The engineers grapple with communicating and resolving the issues. These are skilled teams of engineers working overtime to get things done. Closure always seems a few days away, but continues to elude them.
This is the reality of physical design today and it will only get more difficult as chip complexity and data size continues to grow. In the past, teams sought new tools to deal with the additional technology challenges of a new process node. But even with the latest tools to place the design faster, make better clock-trees, etc., the fundamental problem of organizing the globally distributed team to push through the unknowns remains as the biggest risk to chip success.
Every run through the physical design flow can generate hundreds of GBs of data. Data is not the problem; lack of information is. Extracting meaning from the vast pools of enterprise data is exceedingly complex, and impossible without tool support. What were the metrics of the design two weeks ago? How much change did that last ECO actually introduce into the netlist? These questions point the way to critical improvements today, but finding the information that you need to answer them must be made more practical.
Every member you add to a team exponentially increases the number of relationships and the complexity of communication. This is why simply adding people rarely works without also identifying fundamental changes in tools and processes. Teams may need more people, but first and foremost, they need ways to improve team performance and communication, regardless of size and location.
This is the problem that we solve with ENOVIA Pinpoint.
